1. Field of the Invention
The present invention relates to a semiconductor memory device and in particular to a Dynamic Random Access Memory (hereinafter referred to as a DRAM).
2. Description of Related Art
A DRAM cell that stores data using a capacitor has been widely known as a semiconductor memory device. In the DRAM, a precharge operation is carried out to set a potential level of each bit lines to a predetermined level before reading or writing data.
A half VDD precharge method is generally used as the precharge method. A potential level of each bit lines is set to about a half potential of a power supply potential VDD in the half VDD precharge method. As the power supply voltage VDD becomes lower, the level set by the precharge method also becomes lower in these days. Therefore, in the above-mentioned half VDD precharge method, it is difficult for a sense amplifier to amplify a difference of potential between bit lines potential with high accuracy, because the precharged level is close to a threshold level of the sense amplifier.
In order to deal with the above mentioned problem, a technique to set the precharge level to the ground potential GND has recently become popular. This technique to precharge the bit line to GND level is disclosed in Japanese Unexamined Patent Application Publication No. 2004-265533.
FIG. 8 shows a circuit diagram of the DRAM cell that performs the GND precharge operation. A pair of bit lines BT and BN is shown in FIG. 8. In the circuit shown in FIG. 8, a memory cell (hereinafter referred to as a main cell) CELLT and a reference cell (hereinafter referred to as a ref-cell) CELLRef are connected to each of the bit line pair BT, BN respectively. The main cell CELLT stores a real data. The ref-cell CELLRef outputs a reference voltage. A precharge circuit PRE and a sense amplifier SA are connected between the bit line pair BT, BN.
With reference to FIG. 9, an operation of the circuit shown in FIG. 8 is explained. Before a readout operation, the bit line pair BT, BN is precharged to the ground potential GND. When word lines WL, WR are raised to a predetermined potential, the main cell CELLT and the ref-cell CELLRef start to discharge the stored charge to the bit lines BT, BN. At this time, the ref-cell CELLRef outputs a voltage of around a half level of a voltage corresponding to H level voltage output from the main cell CELLT. This makes it possible to perform normal sensing operation even if L level is stored in the main cell CELLT.
Next, the sense amplifier SA is activated by a sense amplifier drive signal SE. The sense amplifier SA amplifies a difference in voltage of the bit line pair to perform readout operation and so on. After this operation of readout and so on, the bit line pair is precharged to GND again. This GND precharge operation is performed by the precharge circuit PRE. The precharge circuit PRE starts to perform the GND precharge operation when a precharge signal PDL is raised to a predetermined potential. During this precharge operation, a word line WRP is raised to a potential which is higher than the power supply potential. The ref-cell CELLRef is connected to a power source circuit outputting a voltage of ½ VDD via a transistor formed inside the ref-cell CELLRef. Note that the power source to which the reference cell is connected is different from a power source for the bit lines BT, BN.
As a result of this operation, about half of charge stored in the ref-cell CELLRef is discharged even if the bit line BN is set to H level by the sense amplifier SA during the readout operation and the ref-cell stores charge enough for H level. In this way, the ref-cell CELLRef outputs around a half voltage against the H level voltage output from the main cell CELLT during the readout operation, as a result of connecting the ref-cell CELLRef with ½ VDD during the precharge operation.
In the DRAM cell according to the above-mentioned GND precharge method, each of the three word lines WL, WR, and WRP is required to be raised in potential at every reading or writing operation. When the memory cell is charged or discharged to the power source voltage H level, it is required to apply a voltage higher than the power source voltage against a gate of a transistor of the memory cell. Therefore, it is needed to activate a voltage-boosting circuit for raising the potential level of the three word lines, thereby increasing an amount of current consumption.
It is also required for the ref-cell CELLRef to output a voltage around half of the H level voltage output from the main cell CELLT so as to make the sense amplifier operable. But, there are cases where a voltage output from the ref-cell CELLRef is not enough for the sense amplifier to operate with high stability because of an tolerance of the capacitance of the main cell CELLT and the ref-cell CELLRef.
In case of using the GND precharge method, an amount of current consumption is increased, and it is difficult to make the sense amplifier operable with high stability because of the tolerance between circuit elements.